samna.speck2eTestBoard#

Submodules#

Module content#

class samna.speck2eTestBoard.MeasurementChannels#

Bases: pybind11_object

Members:

Io

Ram

Logic

PixelDigital

PixelAnalog

property name#
class samna.speck2eTestBoard.PowerModule#

Bases: pybind11_object

A handle which offers basic power api.

get_adc_core(self: samna.speck2eTestBoard.PowerModule) samna.unifirm.adc.ads1119.Ads1119#
get_adc_io(self: samna.speck2eTestBoard.PowerModule) samna.unifirm.adc.ads1119.Ads1119#
set_vdd_io(self: samna.speck2eTestBoard.PowerModule, arg0: float) None#

Set IO Power Supply

set_vdd_logic(self: samna.speck2eTestBoard.PowerModule, arg0: float) None#

Set Digital Power Supply

set_vdd_pixel_analog(self: samna.speck2eTestBoard.PowerModule, arg0: float) None#

Set Pixel Field Analog Power Supply

set_vdd_pixel_digital(self: samna.speck2eTestBoard.PowerModule, arg0: float) None#

Set Pixel Field Digital Power Supply

set_vdd_ram(self: samna.speck2eTestBoard.PowerModule, arg0: float) None#

Set SRAM Power Supply

class samna.speck2eTestBoard.Speck2eTestBoard#

Bases: pybind11_object

Composite object that allows access to all the board features of a Speck 2e testboard.

get_board_serial_number(self: samna.speck2eTestBoard.Speck2eTestBoard) str#

Get the serial number of the board.

Returns:

The board serial number.

get_dac(self: samna.speck2eTestBoard.Speck2eTestBoard) samna.unifirm.dac.dac7678.Dac7678#
get_edge_detection_module(self: samna.speck2eTestBoard.Speck2eTestBoard) samna.unifirm.modules.edgeDetection.EdgeDetectionModule#
Returns:

A handle to an EdgeDetectionModule object providing a source node to output pulse detection events.

get_firmware_versions(self: samna.speck2eTestBoard.Speck2eTestBoard) samna.boards.common.FirmwareVersions#

Get the Fxtree and Unifirm versions of this board.

get_io_module(self: samna.speck2eTestBoard.Speck2eTestBoard) samna.speck2eTestBoard.UnifirmModule#
Returns:

A handle to the unifirm IO module. Useful in debug scenarios.

get_model(self: samna.speck2eTestBoard.Speck2eTestBoard) samna.speck2e.Speck2eModel#

Get the model of the Speck 2e device on this board.

Returns:

Speck2eModel

get_model_sink_node(self: samna.speck2eTestBoard.Speck2eTestBoard) samna.DeviceSinkNode_speck2e_event_speck2et_input_event | samna.DeviceSinkNode_speck2e_event_speck2e_input_event#

Convenience function to get the model sink node directly

get_model_source_node(self: samna.speck2eTestBoard.Speck2eTestBoard) samna.DeviceSourceNode_speck2e_event_output_event#

Convenience function to get the model source node directly

get_power_module(self: samna.speck2eTestBoard.Speck2eTestBoard) samna.speck2eTestBoard.PowerModule#
Returns:

A handle to an PowerModule object which is used to control power trace voltage and measure power consumption.

get_power_monitor(self: samna.speck2eTestBoard.Speck2eTestBoard) samna.boards.common.power.PowerMonitor#
Returns:

A handle to an PowerMonitor object which is used to read power.

get_reader_writer(self: samna.speck2eTestBoard.Speck2eTestBoard) unifirm::UnifirmReaderWriter#
get_stop_watch(self: samna.speck2eTestBoard.Speck2eTestBoard) samna.unifirm.timestamp.StopWatch#
Returns:

A handle to the stopwatch object to control timestamp in events, for debug purpose. See StopWatch

get_usb_controller(self: samna.speck2eTestBoard.Speck2eTestBoard) samna.fxtree.FxTreeDevice#
Returns:

A handle to an FxTreeDevice object which is used to control the Cypress SuperSpeed USB 3.0 peripheral controller. It it mainly used for debugging.

read_write(self: samna.speck2eTestBoard.Speck2eTestBoard) None#
reset_board_soft(self: samna.speck2eTestBoard.Speck2eTestBoard, arg0: bool) None#

Reset the FPGA and reset the peripherals. Select where the configuration comes from for the Speck 2e chip (External flash or PC).

Parameters:

bootFromPc (bool) – False if there is an external flash contains valid data, otherwise it has to be set to True.

reset_model(self: samna.speck2eTestBoard.Speck2eTestBoard, arg0: bool) None#

Reset the Speck 2e chip and select where the configuration comes from (External flash or PC).

Parameters:

bootFromPc (bool) – False if there is an external flash contains valid data, otherwise it has to be set to True.

start_reader_writer(self: samna.speck2eTestBoard.Speck2eTestBoard) None#
stop_reader_writer(self: samna.speck2eTestBoard.Speck2eTestBoard) None#
class samna.speck2eTestBoard.UnifirmModule#

Bases: pybind11_object

The control of the Speck 2e IO module inside the FPGA. The main clock, SPI clock, slow clock and JTAG clock can be controlled. You could also control the five powers individually and assert/deassert the Speck 2e chip.

assert_reset(self: samna.speck2eTestBoard.UnifirmModule) None#

Assert reset of the Speck 2f.

deassert_reset(self: samna.speck2eTestBoard.UnifirmModule) None#

Deassert reset of the Speck 2f.

enable_asi_interface(self: samna.speck2eTestBoard.UnifirmModule) None#

Enable the ASI interface. Internal debug only.

enable_jtag(self: samna.speck2eTestBoard.UnifirmModule, arg0: bool) None#

Enable JTAG interface, internal debug only. Default disabled.

Parameters:

enable (bool) – True to enable the JTAG interface, False disable it.

enable_power(self: samna.speck2eTestBoard.UnifirmModule, arg0: int) None#

Controls the enable/disable of the five power traces (VDD_IO, VDD_RAM, VDD_LOGIC, VDD_PIXEL_DIGITAL, VDD_PIXEL_ANALOG). These five channels are controlled by the lower five bits respectively, 1 means enable and 0 means disable. Default all enabled.

Parameters:

channel (int) – the channels to be enable/disabled.

pulse_in_out_interface_clk(self: samna.speck2eTestBoard.UnifirmModule) None#

Generate one pulse of the main clock. Internal debug only.

pulse_slow_clk(self: samna.speck2eTestBoard.UnifirmModule) None#

Generate one pulse on the external slow clock. This is useful if you want to manually control the computation of the READOUT block, CNN layer leakage block or DVS filter block. If you want those blocks to perform one computation, just invoke this method one time.

reset_through_registers(self: samna.speck2eTestBoard.UnifirmModule) None#

Reset the Speck 2f through registers. Internal debug only.

set_dual_channel_output_enable(self: samna.speck2eTestBoard.UnifirmModule, arg0: bool) None#

Enable the dual channel output feature. This could improve the output bandwidth if you have extremely high output throughput. Otherwise it may decrease the performance. Default disabled. Note you should control this feature through the monitor_dual_channel, instead of invoking this method directly!

Parameters:

enable (bool) – True to enable this feature, False to disable it.

set_in_out_interface_clk(self: samna.speck2eTestBoard.UnifirmModule, arg0: bool) None#

Enable/disable the main clock (IO interface clock). Default enabled. The main clock is essential to Speck 2f, it must be enable otherwise you can’t use the chip.

Parameters:

onOff (bool) – True to enable the main clock, False to disable the main clock.

set_in_out_interface_clk_rate(self: samna.speck2eTestBoard.UnifirmModule, arg0: int) None#

Set the main clock (IO interface clock). Default is 25Mhz. Maximum 25Mhz.

Parameters:

clock (int) – clock in Hz.

set_jtag_clk_rate(self: samna.speck2eTestBoard.UnifirmModule, arg0: int) None#

Set the JTAG clock rate in Hz. Internal debug only.

Parameters:

frequency (int) – JTAG clock in Hz.

set_slow_clk(self: samna.speck2eTestBoard.UnifirmModule, arg0: bool) None#

Enable/disable the external slow clock. Default disabled. The slow clock can used with the Readout block, CNN layer leakage block and DVS filter block.

Parameters:

onOff (bool) – True to enable the slow clock, False to disable it.

set_slow_clk_rate(self: samna.speck2eTestBoard.UnifirmModule, arg0: int) None#

Set the external slow clock rate in Hz. Default 1000Hz.

Parameters:

frequency (int) – slow clock rate in Hz.

set_spi_clk_rate(self: samna.speck2eTestBoard.UnifirmModule, arg0: int) None#

Set CPI clock rate in Hz, which can not exceeds 1/16 of the main clock. Default 1.5625Mhz.

Parameters:

freq (int) – clock rate in Hz.

write_config(self: samna.speck2eTestBoard.UnifirmModule, arg0: int, arg1: int) None#

Write raw configuration for IO module, internal debug only.

Parameters:
  • addr (int) – the IO module register address

  • value (int) – value to be written